1. Field of the Invention
The present invention relates to an image information transmission system capable of encoding and transmitting image information with a high efficiency.
2. Related Background Art
Among such image information transmitting methods, there is already known, for example, a high efficiency encoding method for the television signal. In order to limit the transmission band width, said method employs the so-called min-max method which reduces the average number of bits per pixel. This min-max method will be described in the following.
The television signal has a strong time-space correlation. When an image is divided into small blocks, each block usually has a relatively small dynamic range due to the local correlation. Consequently, highly efficient information compression is possible by determining the dynamic range in each block and effecting adaptive encoding.
In the following this encoding method will be explained further, with reference to the attached drawings.
FIG. 1 schematically shows an image information transmitting system, as an example of prior technology. An input terminal 101 receives digital image data obtained by sampling a raster-scan analog image signal such as a television signal with a predetermined sampling frequency to obtain data of n bits per sample. Said digital image data of 2.sup.n levels are supplied to a pixel block dividing circuit 102.
FIG. 2 shows the mode of division of pixel data of a frame into pixel blocks. The pixel block dividing circuit 102 stores all the pixel data of a frame into a memory, and reads said pixel data in units of pixel blocks composed of l pixels in the horizontal (H) direction and m pixels in the vertical (V) direction. Thus the data are released units of pixel blocks.
FIG. 3 shows the structure of each pixel block, wherein D.sub.1,1 - D.sub.m,1 represent respective pixel data. The image data released from the pixel block dividing circuit 102 are supplied to a maximum detecting circuit 103, a minimum detecting circuit 104 and a timing regulating or adjusting circuit 105, whereby the maximum datum (Dmax) and the minimum datum (Dmin) are detected by the detecting circuits 103, 104, from among all the pixel data (D.sub.1,1 - D.sub.1,m) in each pixel block.
The timing adjusting circuit 105 delays all the pixel data by a time required by the maximum detecting circuit 103 and the minimum detecting circuit 104 for detecting Dmax and Dmin, and sends, to a divided value converting circuit 106, the pixel data of each pixel block in a predetermined order, for example D.sub.1,1, D.sub.2,1, D.sub.3,1..., D.sub.m,1, D.sub.1,2, ..., D.sub.m,2, ..., D.sub.1,(l-1), ..., D.sub.m,(l-1), D.sub.1,1, ..., D.sub.m,1.
In this manner, all the pixel data (D.sub.1,1 - D.sub.m,1) in each pixel block and the maximum value (Dmax) and the minimum value (Dmin) are supplied to the divided value converting circuit 106, and there is obtained a division code of k bits (.DELTA..sub.1,1 - .DELTA..sub.m,1) determined by comparison of each pixel datum with 2.sup.k digitizing levels defined between Dmax and Dmin, wherein k is an integer smaller than n. The mode of this digitization is shown in FIG. 4A.
As shown in FIG. 4A, the code .DELTA..sub.i,j is released as a binary code of k bits. The division codes .DELTA..sub.i,j of k bits and, Dmax and Dmin of n bits thus obtained are respectively supplied to parallel-to-serial converters 107, 107', 107" for conversion into serial data, and further converted in a data selector 108 into serial data as shown in FIG. 5, illustrating the transmission data for a pixel block.
The data from the data selector 108 are subjected to a time-axis treatment for obtaining a fixed data transmission rate in a first-in-first-out (FIFO) memory 109, then subjected to the addition of a synchronization signal in a synchronization adding circuit 110, and sent, from an output terminal 111, to a transmission channel, for example a magnetic recording reproducing system of a video cassette recorder. The synchronization signal may be added to every pixel block or every predetermined number of pixel blocks. The function timing of the above-described circuits is determined according to timing signals released from a timing control circuit 112.
FIG. 6 schematically shows the receiving circuit, constituting a counterpart of the data transmission circuit shown in FIG. 1. An input terminal 121 receives the transmission data subjected to high efficiency transmission in the transmitting circuit described above. The synchronization signal in the entered transmission data is separated by a synchronization separating circuit 122 and is supplied to a timing control circuit 123, which determines the function timing of various portions of the receiving circuit according to said synchronization signal.
On the other hand, a data selector 124 separates the transmission data into data Dmax, Dmin of n bits and codes .DELTA..sub.i,j obtained by digitizing each pixel data into k bits between Dmax and Dmin. These separated data are respectively converted into parallel data by serial-to-parallel converters 125, 125'. The maximum datum Dmax and the minimum datum Dmin in each pixel block, converted into parallel data by the converter 125, are respectively latched by latch circuits 126, 127, and said latch data Dmax, Dmin are supplied to a divided value inverse converting circuit 128. On the other hand, the division codes .DELTA..sub.i,j representing the pixel data in each pixel block are released in the aforementioned order from the serial-to-parallel converter 125' and supplied to the divided value inverse converting circuit 128.
FIG. 4B illustrates the mode of restoring representative data D'.sub.i,j relating to the original pixel data, from the division code .DELTA..sub.i,j and the values Dmax, Dmin. The representative values are set, for example, at the middle of the digitizing levels which divide the area between Dmax and Dmin into 2.sup.k zones. The representative values of n bits (D'.sub.1,1 - D'.sub.m,1) obtained from the divided value inverse converting circuit 128 are released in the aforementioned order for each pixel block. A scan converter 129 converts the output data of the divided value inverse converting circuit 128 into an order corresponding to raster scanning, and sends the thus obtained decoded image data to an output terminal 130.
It is to be noted, however, that the prior technology described above only utilizes the correlation of image in the two-dimensional space. Consequently the transmitted information contains redundancy in the time axis if a still image or images with limited movement are transmitted. In such case the efficiency of transmission deteriorated as the same information is transmitted repeatedly.